An exemplary embodiment relates generally to a method of manufacturing a nonvolatile memory device and, more particularly, to a method of forming a nonvolatile memory device that is capable of preventing damage to gate patterns in a process of forming trenches.
A nonvolatile memory device includes a memory cell array area and a peripheral area. A number of string structures are formed in the memory cell array area. Each of the string structures includes a number of memory cells coupled in series between a source select transistor and a drain select transistor and configured to store data. The string structures are spaced apart from each other with an isolation layer interposed therebetween. The isolation layer is formed in the isolation area of a semiconductor substrate. In the peripheral area are formed circuit elements, such as a power source circuit and a control circuit for controlling the program, erase, and read operations of a memory cell. The circuit elements further include a low-voltage or high-voltage NMOS transistor and a PMOS transistor.
In a NAND flash memory device advantageous for a high degree of integration, the gate patterns of memory cells include polysilicon layers used as charge trap layers. The polysilicon layers used as the charge trap layers are formed as patterns separated from each other for every memory cell. To form the polysilicon layers in the form of patterns separated from each other for every memory cell, a trench formation process of defining areas in which the isolation layers will be formed can be used. If, as described above, the polysilicon layers used as the charge trap layers are patterned using the trench formation process, there is an advantage in that error occurring when the charge trap layers and the isolation areas are aligned can be improved. The method of patterning the polysilicon layers, used as the charge trap layers, using the trench formation process is described below with reference to FIG. 1.
FIG. 1 is a cross-sectional view of the memory cell array area and the peripheral area of a nonvolatile memory device. In particular, FIG. 1 shows part of an area in which memory cells is formed, from among a memory cell array area and part of an area in which a high-voltage circuit element is formed, from among a peripheral area.
Referring to FIG. 1, a number of the memory cells and circuit elements are formed over the active areas of a semiconductor substrate 11, defined by trenches 19. The trenches 19 are formed by etching the semiconductor substrate 11 and are configured to define isolation areas and the active areas. The isolation area is an area in which the trench 19 has been formed and an isolation layer will be formed in a subsequent process. The active area is an area in which the trench 19 has not been formed. Thus, the active areas are separated from each other with the trench 19 interposed therebetween and defined between the trenches 19 in parallel to the trenches 19.
A process of forming the trenches 19 is described in detail below. First, a gate insulating layer 13, a polysilicon layer 15 for a charge trap layer, and an isolation hard mask pattern 17 are stacked over the semiconductor substrate 11. The polysilicon layer 15, the gate insulating layer 13, and, the semiconductor substrate 11 are sequentially etched by an etch process using the isolation hard mask pattern 17 as an etch barrier. The trench 19 is formed in an opened area between isolation hard mask patterns 17 of the semiconductor substrate 11. The polysilicon layer 15 and the gate insulating layer 13 remain in an area between the semiconductor substrate 11 and the isolation hard mask pattern 17.
The etch process using the isolation hard mask pattern 17 as an etch barrier can be simultaneously performed on the peripheral area and the memory cell array area. In the process of etching the semiconductor substrate 11 using the isolation hard mask pattern 17 as the etch barrier, the sidewalls of the polysilicon layer 15 are already exposed. Accordingly, an etchant used when the semiconductor substrate 11 is used can infiltrate into the polysilicon layer 15, and so the sidewalls X of the polysilicon layer 15 can be etched. The excessive etch of the sidewalls X of the polysilicon layer 15 results in device failure.